AXI vs AHB

AHB : Advanced High performance Bus
AXI : Advanced Xtensible Bus

 

AHB의 주요 문제는 Outstanding Transaction(미해결 트랜잭션이 발행되었지만 응답을 기다리는) 지원이 안되는 것이다. 

Write는 Response 필수가 아니지만 대부분의 Read는 Response가 필요하다.

 

Response 없이 Outstanding Transaction을 여러 개 발행하면 처리량을 높일 수 있다.

 

AXI는 data 전송의 Duplex 모드를 가능하게 하는 R/W위한 독립적인 채널을 가지고있다. 예를 들어 Dual port SRAM에서 한쪽은 Read 한쪽은 Write 동시에 진행할 수 있다. 

마스터가 1개 슬레이브가 1개인 시스템에서는 성능차이가 없고 AXI는 더 많은 전력과 면적만 소비한다. 시스템에 맞춰 선택하야함.

 

 

AXI의 경우 OT를 발행할 수 있어서 데이터의 응답을 기다리지 않고 발행하여 초기 delay만 있고 데이터의 지속적인 흐름이 가능하다. AHB는 OT가 없어서 처리될 떄까지 대기가 필요.

 

결론 : AHB가 속도가 느려도 되고 작은 시스템에서만 사용되고 여러 Clock domain, 고속, 처리량 및 대역폭 요구가 높을때 사용

 

 

AHB	AXI
1 address channel 1 read data channel 1 write data  channel	1 read address channel 1 write address channel 1 read data channel 1 write data channel 1 write response channel That is altogether it has 5 parallel channels
Does not support outstanding reads	support for multiple outstanding transactions
No concept of channels	AXI supports transaction IDs
does not support pipeline registers in its path, if user is not able to meet timing requirements.	User can insert a pipeline register anywhere in the path of any of the 5 channels, which helps in timing closure and help achieve higher operating frequency.
Due to its in-ability to support pipeline registers insertion, AHB limits the max freq for the design. This can hit hard, on the SoCs which are big, and may have long distances for the datapath to cover.	AXI enables higher frequency of operation due to its support for 'pipe-line' register insertion.
Number of wires are less	Since AXI has 5 parallel channels running, it has a lot of more wires, which may cause congestion in layout.
Limited Throughput.	Extremely high Throughput
No inherent support for side-band signals	AXI 4 supports AxUSER bits, i.e. it has support for side-band signals.
No QoS Support	AXI 4 supports QoS

Burst Lengths are fixed i.e 1, 2, 6, 16 except for INCR types, where it can be anything as long as it does not cross 4K boundary.	Burst lengths can be anything, from 1-16 for AXI3, and 1-256 for AXI4.
The 'INCR' type burst can have any length, but there is no information available at the start of the burst, how long it might be.	The length of the burst is always known right at the start. This feature is supported by using AxLEN bits.
Low power dissipation	Higher power dissipation. 50% 더 소비
Write Strobes are not supported.	Write Strobes Are supported
Locked Transfers are supported	AXI3 supports Locked Transfers, AXI4 does not support Locked Transfers.
Exclusive transfers are Not Supported	Exclusive transfers are supported.
Strongly Ordered: Since there is at a time only 1 active transactions, the transactions are strongly ordered in the sense, that the responses received to any transaction(s) follow the same sequence as the transactions were issued.	Since it supports multiple outstanding transactions, i.e. many transaction is issued at a time, the responses to different transactions can arrive out of order. However the responses to each 'channel' will still be ordered, i.e to say responses with same ID must return in order